銆€銆€銆�鍎€琛�缍�(w菐ng) 鐮旂櫦(f膩)蹇▕銆戝叿鏈夐珮闁嬮棞(gu膩n)姣斻€佷綆浜為柧鍊兼摵骞呯殑楂樻€ц兘钖勮啘鏅堕珨绠� (TFT)鍣ㄤ欢锛屾槸闁嬫嫇鏂颁竴浠ｅぇ闈㈢⿳楂樻竻椤ず銆佹煍鎬ч浕瀛�/鍌虫劅鍜岃叇姗�(j墨)鎺ュ彛鎳�(y墨ng)鐢ㄧ殑鎶€琛�(sh霉)闂�(gu膩n)閸�銆傚叾涓紝瓒呯窗(x矛)銆佽秴鐭櫠纭呯磵绫崇窔婧濋亾锛岀敱浜庡叿鏈夎壇濂界殑鏌垫帶鍜屽ぇ闆绘祦椹�(q奴)鍕�(d貌ng)鑳藉姏锛屾垚鐐烘(g貌u)寤洪珮鎬ц兘TFT鍣ㄤ欢鐨勭悊鎯崇祼(ji茅)妲�(g貌u)銆傞洊鐒舵椤炵簿绱�(x矛)婧濋亾绲�(ji茅)妲�(g貌u)鍦�“寰�”闆诲瓙鍣ㄤ欢宸ヨ棟涓凡鎴愮偤涓绘祦锛屼絾鍗讳緷璩村湪纭呮櫠鍦撲笂鐨勮秴楂樼簿搴︽繁绱/妤电传澶栧厜鍒� (D/EUV)鍜屽埢铦曟妧琛�(sh霉)锛屽洜姝ょ劇(w煤)娉曞湪澶ч潰绌�“瀹�”闆诲瓙鍣ㄤ欢鐨勫ぇ灏哄鐜荤拑鎴栬仛鍚堢墿瑗簳涓婃噳(y墨ng)鐢�銆傚浣曞熀浜庢湁闄愮殑鐔遍爯(y霉)绠�(<500鈩�)鍜岃純浣庣殑鍏夊埢绮惧害(>1.5 μm)锛岄泦鎴愬埗鍌欑洿寰戝皬浜�30 nm銆侀暦(zh菐ng)搴﹀皬浜�100 nm鐨勭簿绱�(x矛)绱嶇背婧濋亾锛屾垚鐐洪枊鎷撴柊涓€浠ｉ珮鎬ц兘TFT鍣ㄤ欢鎵€闈㈣嚚鐨勯棞(gu膩n)閸垫妧琛�(sh霉)鐡堕牳銆�
 

銆€銆€閲濆皪(du矛)閫欎竴鎸戞埌(zh脿n)锛屽崡浜ぇ瀛�(xu茅)浣欐灄钄氭暀鎺堛€佺帇杌嶈綁(zhu菐n)鏁欐巿鍜屾彋(y谩ng)宸炲ぇ瀛�(xu茅)鑳＄憺閲戣€佸斧锛屽熀浜庤嚜涓诲壍(chu脿ng)鏂扮殑闈㈠収(n猫i)鍥�-娑�-鍥�(IPSLS) 绱嶇背绶氱敓闀�(zh菐ng)妯″紡锛岄娆℃彁鍑哄埄鐢ㄥ偓鍖�“娑叉淮闅庤烦”鐢熼暦(zh菐ng)鍕�(d貌ng)鎱�(t脿i)锛屾垚鍔熷(sh铆)鐝�(xi脿n)瓒呯窗(x矛)銆佽秴鐭櫠纭呯磵绫崇窔婧濋亾闄ｅ垪鐨勫彲闈犻泦鎴愬埗鍌欍€傚叿楂旇€岃█锛屽熀浜嶪PSLS鐢熼暦(zh菐ng)妯″紡鐨勪綆婧畾浣嶇敓闀�(zh菐ng)(<350鈩�)鑳藉姏锛屽皣鍌寲娑叉淮绮剧⒑寮曞皫(d菐o)鐢熼暦(zh菐ng)鍒拌烦韬嶄氦鍙夎嚭(t谩i)闅庨倞绶�锛岄€氶亷(gu貌)鎺у埗鏌旀€ф恫婊磋法瓒婅嚭(t谩i)闅庣殑“Step-Necking鏀剁府”鏁堟噳(y墨ng)锛屽湪鑷�(t谩i)闅庨倞绶ｄ竴姝ユ垚褰㈠湴鐢熼暦(zh菐ng)鍑烘墍闇€鐨凾hick(45nm)/Thin(25nm)/Thick(45nm)瓒呯簿绱�(x矛)婧濋亾绲�(ji茅)妲�(g貌u)锛屽叾涓秴绱�(x矛)婧濋亾闀�(zh菐ng)搴﹀儏鐐篖(zh菐ng)g~90 nm锛屽苟涓斿湪鍏╃绮楃窔鎻愪緵浜嗚嚜鐒剁殑鐞嗘兂S/D鎺ヨЦ—瀹屽叏椤炰技浜庤垏鍏堥€�(j矛n)榘煹鏅堕珨绠� (Fin-FET) 涓悊鎯虫簼閬撳拰S/D鎺ヨЦ鏋舵(g貌u)銆�
 

鍦�1 闋哥府鐢熼暦(zh菐ng)纭呯磵绫崇窔闄ｅ垪鍘熺悊鍙婃祦绋嬩互鍙婄绱嶇背绶氶櫍鍒楀舰璨屽強鍏剁洿寰戠当(t菕ng)瑷�(j矛)銆�
 

銆€銆€鍙楃泭浜庢锛孲tep-Necking 绱嶇背绶歍FT鍣ㄤ欢灞曠ず浜嗗劒(y艒u)鐣扮殑鏌垫帶鏁堟灉鍜屽ぇ骞呮敼鍠勭殑杓搁亱(y霉n)鐗规€�锛屽(sh铆)鐝�(xi脿n)浜�
 

鍦�2 鍩轰簬闋哥府纭呯磵绫崇窔鐨勯珮鎬ц兘鏅堕珨绠″櫒浠�銆�
 

銆€銆€瑭插伐浣滆繎鏈熶互“Step-necking growth of silicon nanowire channels for high performance field effect transistors”鐐洪鐧�(f膩)琛ㄥ湪鑷劧-閫氳▕銆奛ature Communications銆嬫湡鍒婁笂銆傛枃绔犵涓€浣滆€呯偤鍗椾含澶у(xu茅)闆诲瓙绉戝(xu茅)鑸囧伐绋嬪(xu茅)闄㈢殑鍗氬＋鐢熷惓纾�锛屼綑鏋楄敋鏁欐巿銆佽儭鐟為噾鑰佸斧銆佺帇杌嶈綁(zhu菐n)鏁欐巿鐐烘枃绔犲叡鍚岄€氳▕浣滆€�銆傝┎宸ヤ綔鐨勯枊灞曞緱鍒颁簡鍗椾含澶у(xu茅)闄冲潳鍩烘暀鎺�銆佸緪椐挎暀鎺�銆佹柦姣呮暀鎺堟敮鎸佸拰鎸囧皫(d菐o)锛屽彈鍒板湅(gu贸)瀹堕噸榛�(di菐n)鐮旂櫦(f膩)瑷�(j矛)鍔�銆佸湅(gu贸)瀹惰嚜鐒剁瀛�(xu茅)鍩洪噾鏉板嚭闈掑勾瀛�(xu茅)鑰呴爡(xi脿ng)鐩互鍙婂湅(gu贸)瀹惰嚜鐒剁瀛�(xu茅)鍩洪噾閲嶉粸(di菐n)闋�(xi脿ng)鐩殑璩囧姪銆�